Backend
AMD openSIL Achieves Its Production Goal With 6th Gen EPYC "Venice"
Phoronix0 views
Since 2023 I and many open-source advocates have been very eager for AMD's openSIL project for delivering open-source CPU silicon initialization as a replacement to the traditional AGESA code. With Zen 5 there was proof-of-concept support that we have enjoyed with Coreboot on an MSI Ryzen motherboard and a Gigabyte EPYC server motherboard thanks to the Coreboot-based Dasharo ports by 3mdeb. The goal for production readiness was for Zen 6, but with this week's EPYC 9006 SP7 announcement the openSIL topic wasn't touched on. So I asked around...
Source:https://www.phoronix.com/news/AMD-openSIL-Venice-GoalPreviousThere's 50% off Criterion Collection 4K Blu-rays — here are my 9 picksNextKDE Frameworks 6.32 Released With That Fix For USB File Transfer Notifications
Related posts

YouTube App Not Working on Your New Apple TV? Here's the Fix
0MacRumors
iPhone Duo Survives 450,000 Folds, but Hinge is Weakening
0MacRumors
Show HN: Giving frontier AI models capital and access to onchain markets
0Hacker News Show

Connect Google Wallet to Gemini for personal finance insights
0Google Blog
New AI 'copilot' lets engineers guide structural designs as algorithms create them
0Phys.org Tech
Deploying an Axum service on a Canadian VPS
0Rust Users Forum