It is not official NXP, IPC, or microcontroller documentation, and it does not certify a board. Formulas below are those published on the tool pages, checked against the usual textbook identities; a couple of worked examples on the site do not match those identities, and those examples are not repeated here.

Firmware and hardware people reach for browser calculators when a pull-up “usually works,” a debug UART is slightly corrupt, or a power trace looks narrow. Each problem has a published formula, assumptions, and things the formula cannot see: integer dividers, unmeasured bus capacitance, copper that is not exactly one ounce, and the far end of a serial link.

ResiCalc is an independent educational site of free, client-side electronics calculators. Its about page says results are for engineering guidance and should be verified against datasheets and standards for critical designs. Treat them as transparent first calculations, not as a finished sign-off.

I²C pull-ups: a window, not a single resistor

I²C is an open-drain (or open-collector) bus: devices can pull SDA or SCL low, but the high level comes from a pull-up to the segment’s VCC. ResiCalc’s I²C pull-up resistor calculator is built around two bounds that appear in the usual I²C design notes.

The lower bound is set by how much current a driver must sink when the bus is low:

Rp_min = (Vcc − Vol_max) / Iol

The page takes the familiar typical Iol of 3 mA. If the pull-up is too strong, a driver cannot reach a valid low. The upper bound is set by rise time. The published maximum is

Rp_max = tr / (0.8473 × Cb)

The constant 0.8473 is ln(0.7/0.3): the interval, in units of the RC time constant, between 30% and 70% of a rising exponential toward VCC, which is the rise-time window used in the I²C specification’s RC model. If you accept that model, the formula is the right inversion. Cb is the total bus capacitance — devices, connectors, and traces — and tr is the allowed rise time for the selected mode: Standard (100 kHz), Fast (400 kHz), or Fast+ (1 MHz).

The notes suggest 2.2 kΩ–4.7 kΩ as a starting range for many 3.3 V designs, with lower resistance for faster modes, and they describe Standard and Fast mode as keeping bus capacitance under 400 pF. Those typical values are inside the allowed window, not the same thing as Rp_max. For a 50 pF bus and a 1,000 ns Standard-mode rise-time budget, the published Rp_max formula gives on the order of 24 kΩ. A 4.7 kΩ pull-up at 100 kHz is a practical choice, not the mathematical ceiling.

A 10 kΩ pull-up at 400 kHz is often too slow, and capacitance is easy to underestimate if you count only one chip and ignore the cable. Pull-ups at both ends of a long cable, or at every device on a single segment, sit in parallel and can violate the sink-current bound. Mixed 3.3 V and 5 V segments need a level translator; pull-ups go to each segment’s voltage, and a 3.3 V pin is not automatically 5 V tolerant.

The calculator cannot measure your bus. If Cb is a guess, Rp_max is a guess; if a slave’s Vol or Iol differs from the typical 3 mA model, Rp_min moves. For a long, marginally timed bus, a scope on the rising edge is still the right instrument.

UART baud error: the divider has to be an integer

ResiCalc’s UART baud-rate calculator starts from the usual clock-divider relationship:

Baud = Clock / (Oversample × Divider)

and

Error = (Actual − Target) / Target × 100%

The default oversampling factor in the notes is 16×, the classic UART receiver arrangement; some peripherals also offer 8×, with less noise margin. The divider must be an integer on a typical MCU UART, which is the entire source of the systematic baud error: you cannot have 4.34 of a divider, only 4 or 5.

That last point matters because a worked comment on the same page, describing 115,200 baud from an 8 MHz clock as a 4.34 divider, 114,285 baud, and 0.79% error, does not follow from an integer 16× divider. With 16× oversampling, 8,000,000 / (16 × 115,200) is 4.340. Rounding to 4 gives an actual baud of 125,000, which is an 8.51% error — well outside any of the “keep it small” figures the page itself quotes. The 114,285 figure is what you get if you divide 8 MHz by 70, which is not an integer 16× divider of 4. Use the formula, not that particular example.

A cleaner illustration of the same formula: 11.0592 MHz at 16× into 115,200 baud divides exactly by 6, so the error is zero, which is why that crystal family is called UART-friendly. 8 MHz into 9,600 baud at 16× gives a divider of 52.083, and an integer 52 yields 9,615.4 baud, about +0.16%.

How much error is acceptable is not a single law. The ResiCalc page says, in different places, to keep error below ±2%, that exceeding ±3% causes bit errors, and that ±3.5% is an absolute maximum — rules of thumb, not a substitute for the datasheet timing budget. The important structural fact, which the page also states, is that errors at both ends add. A transmitter 1.5% fast and a receiver 1.5% slow are not “fine because each is under 2%.” Framing errors often show up at the stop bit, especially in long packets.

The calculator will also not see logic levels, an uncrossed TX/RX pair, or a clock that is itself off because the crystal load is wrong. It answers one question: given this clock, this oversampling, and this integer divider, how far is the baud rate from the one you named?

Trace width: an IPC-2221-style baseline, not a thermal sign-off

ResiCalc’s PCB trace-width calculator describes an “IPC-style baseline” and documents the IPC-2221 current relationship

I = k × ΔT^b × A^c

with I in amperes, ΔT the temperature rise in °C, and A the cross-section in mil². The constants it lists are the ones commonly quoted from that standard: for external layers, k = 0.048, b = 0.44, c = 0.725; for internal layers, k = 0.024. Copper thickness is entered as a copper weight; the page uses 1 oz = 1.378 mils (35 µm), the usual conversion.

Inverting the published external-layer constants for 1 A, a 10 °C rise, and 1 oz copper gives a cross-section of about 16.3 mil² and a width of about 12 mil (0.30 mm). That is in the same neighborhood as the page’s FAQ figure of “approximately 10 mils,” which it already tells you to round up. Internal layers, with k halved, come out substantially wider — the page’s rule of thumb is about twice, because those traces are buried in laminate.

The site is careful about what this is not. It notes that IPC-2221 is an older, conservative baseline, and that IPC-2152 is the newer chart set, taking better account of board thickness, thermal conductivity, and nearby copper. Use wider traces than the minimum, watch via bottlenecks — a wide trace into a single small via is not a wide trace — and verify critical paths with thermal simulation. Plating can move “1 oz” copper by a sizable fraction, and solder mask is a thermal insulator.

One worked “handbox” example on the same page does not match the formula the page publishes: the arithmetic it prints for 3 A and a 10 °C external rise does not evaluate to the 39.5 mil² or 0.726 mm width it then states. Trust the formula and a fresh evaluation, or the manufacturer’s IPC-2152-based charts, rather than that particular boxed result.

A browser page also cannot see your stackup, enclosure rise, or current crowding at a connector pad. ΔT is a rise above the ambient you assumed: a 10 °C rise in a 50 °C box is a 60 °C trace. Do not invent a margin to the laminate’s glass-transition temperature without the datasheet.

Use the formula, print the assumption

The common thread is to read the assumption next to the result. An I²C resistor is a window set by sink current and rise time, and the window moves with a capacitance you may not have measured. A UART divider is an integer, and both ends of the link share the error budget. A trace width from IPC-2221-style constants is a baseline current-versus-temperature-rise estimate, not a fire-safety or EMC sign-off. ResiCalc’s value, on these three pages, is that the formulas are written down and the common mistakes are mostly the real ones. That is enough to make them a good second check — and not enough to skip the datasheet, the scope, or, for a high-current or safety-related board, a proper review.