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Core-Lock Scheduling for 5G NR LDPC Decoders
arXiv eess.SP0 views
arXiv:2611.08400v1 Announce Type: new Abstract: Accelerating iterative LDPC decoding while preserving error-correction reliability is a critical challenge in latency-constrained 5G New Radio (NR) and non-terrestrial networks. This paper proposes a hardware-efficient core-lock scheduling mechanism that evaluates the core syndrome weight after each layer update to selectively bypass extension layers. With the selected threshold $\theta{=}0.20$, the mechanism reduces decoding latency by up to 31.3\% when integrated with static schedules, and by up to 45.5\% compared to alternative dynamic schemes utilizing the full parity-check matrix, without block error rate (BLER) degradation. Compared with an estimated fully parallel full-matrix checker, the core-only approach yields a 76\% reduction in shifter network area and a 73\% reduction in XOR gate count. For decoders with existing early termination, the proposed mechanism requires only a compact adder tree and a comparator.
Source：https://arxiv.org/abs/2611.08400PreviousElectromagnetically Consistent Monostatic ISAC Beamforming: Mutual Coupling, Active Mismatch and Tx-Rx Leakage in Compact Dipole ArraysNextSpectral Regimes of Truncated sinc-Power and Pulse-Train Kernels: Edge Exponents, Per-Edge Plunges, and the Landau-Widom Limit
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