arXiv:2610.33107v1 Announce Type: cross Abstract: Hysteresis edge tracking, the final stage of Canny edge detection, follows edge chains of unbounded length and therefore resists single-pass streaming; FPGA designs either approximate it or dedicate separate labelling hardware to it. We show that a single library of hardwired 3x3 operators, each with an identical two-clock latency, delivers both a camera-rate approximation and exact hysteresis on a low-cost Artix-7 (XC7A35T). The fast path streams camera pixels through the operators and K local hysteresis stages and commits each edge decision 262.15-720.63 microseconds after the pixel arrives (K = 1-8; system simulation with a datasheet camera model), that is, 3 + K camera lines later and 46-127x sooner than a frame-based processor can even begin at 30 frames per second. It provably never reports an edge that exact hysteresis rejects, recovers 76.6-96.1% of exact edges at thresholds 20/40, and on the 200 BSDS500 test images retains at least 98.6% of the exact path's boundary F-measure (ODS 0.470-0.477 versus 0.476). The exact path holds 128x128 tiles in block RAM, is exact within each tile, and replaces two-buffer iteration with in-place forward and reverse sweeps built into the same operator. This reduces hysteresis from 38-82 passes to 3-7 on pattern and photo tiles, accelerating the hysteresis step 6.6-21.7x (40x on a worst-case tile) and a complete tile 4.5-9.9x, with identical output. Both paths are bit-exact with software golden models at every pipeline stage and close timing at 50 MHz in at most 1455 LUTs. An optimised multi-core CPU remains faster on stored images, but it cannot begin until the frame is complete.