arXiv:2610.13324v1 Announce Type: new Abstract: In this paper, we propose a signal processing concept, signal processing in networks (SPIN), that executes signal processing tasks directly on programmable switches. Traditionally, signal processing tasks, such as denoising, decomposition, and dimensionality reduction, are performed on edge or cloud servers, i.e., raw streams are transmitted from sensors. This imposes a heavy processing load on edge/cloud servers and requires substantial bandwidth. SPIN addresses this problem by performing signal processing on the forwarding path. As an initial realization of SPIN, we implement a DCT-based block transform on a programmable switch. We redesign its computation using a lifting-based lattice structure, multiplierless approximation, and pipeline partitioning across stages in a programmable switch. We verify at the compiler level that the proposed implementation satisfies the strict hardware constraints of the Intel Tofino2--specifically regarding pipeline stages, packet header vector, and ternary content-addressable memory usage--and therefore enables line-rate processing. We further quantify the per-packet latency of the ingress match-action pipeline. The SPIN-oriented preprocessing adds 46 cycles (approximately 31 ns at 1.5 GHz). The total ingress match-action unit latency is approximately 87 ns, which remains consistent with the low-latency operation targeted by SPIN. Furthermore, we implement the proposed block transform on a BMv2 switch using P4 and evaluate it as preprocessing for in-network machine learning. Experimental results demonstrate that the proposed method improves classification performance over unfiltered baselines.